module Wj_comp (
    input [31:0] Wj_16,
    input [31:0] Wj_9,
    input [31:0] Wj_3,
    input [31:0] Wj_13,
    input [31:0] Wj_6,

    output [31:0] Wj
    
);

wire [31:0] P1;
wire [31:0] X;

//P1(X) = X ⊕ (X ≪ 15) ⊕ (X ≪ 23)
assign P1 = X ^ {X[16:0],X[31:17]} ^ {X[8:0],X[31:9]};
//X = Wj−16 ⊕ Wj−9 ⊕ (Wj−3 ≪ 15)
assign X = Wj_16 ^ Wj_9 ^ {Wj_3[16:0],Wj_3[31:17]};
//Wj = P1(X) ⊕ (Wj−13 ≪ 7) ⊕ Wj−6
assign Wj = P1 ^ {Wj_13[24:0],Wj_13[31:25]} ^ Wj_6;


endmodule //Wj_comp